According to a conventional technique (first conventional technique), when multiple threads are assigned to CPUs of a single-core processor system or multi-core processor system, the order of execution of threads is determined based on priority levels defined for individual threads (see, for example, Japanese Laid-Open Patent Application No. S63-068934).
According to another technique (second conventional technique), when multiple threads are assigned, each of the threads is executed for a given interval sequentially (see, for example, Japanese Laid-Open Patent Application No. 2000-276360 and C. L. Lui, James W. LAYLAND, “Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment”, Journal of the Association for Computing Machinery, Vol. 20, No. 1, January 1973).
The first conventional technique, however, poses a problem that when the power consumed for standby by a low-priority thread among multiple threads is large, power consumption increases. The second conventional technique poses a problem that because threads are switched at each given interval, contention occurs over access of a cache in a CPU in which execution information of each thread is temporarily stored.
For example, during execution of a given thread by the CPU, execution information of the given thread is stored to the cache. When the given thread is switched with another tread to be executed, the execution information of the given thread in the cache is overwritten by execution information for the other thread. Then, when the other thread is switched with the given thread to be executed, the execution information of the other thread in the cache is overwritten by the execution information for the given thread. This process leads to a problem of a decline in execution performance and a decrease in throughput.